A successive approximation register (SAR) analog to digital converter (ADC) is often employed in electronic systems to convert an analog signal into a digital representation of the analog signal via a charge scaling circuit that performs a binary search algorithm and a comparator. The charge scaling circuit generally includes an array of capacitors that is employed to perform the binary search algorithm. The comparator generally compares the analog signal to a signal generated by the charge scaling circuit. However, the comparator can become stalled (e.g., enter a stalled state, enter an undecided state, etc.) when comparing the analog signal to the signal generated by the charge scaling circuit. As such, the comparator can provide inaccurate results and/or the digital representation of the analog signal can be incorrect. Moreover, future comparisons by the comparator can be negatively affected by a stalled comparator.
The above-described description is merely intended to provide a contextual overview of current SAR ADC systems and is not intended to be exhaustive.